Low Power and Ultra-low Power Integrated Circuits Design, Electronic-Photonic Integrated Circuits, Energy-efficient Architecture and Chip Desigin for AI, Computer System Architecture.

Dr. Eric He received his B.S., M.S. and Ph.D. degree in Microelectronics and Solid State Electronics from Harbin Institute of Technology in 1999, 2001, 2005, respectively.

From 2005 to 2006, Dr.He worked for postdoctoral research project at Hong Kong University of Science and Technology. Now, Dr.He is an associate professor in the Department of Micro-Nano Electronics at Shanghai Jiao Tong University.

(1) Adaptive and Dynamic Voltage/Frequency Scaling Techniques for Wide-Supply Voltage System-on-Chip, National Key Research and Development Program of China, 2019-2022, Principal Investigator.
(2) Design Methodology of Ultra-Low Voltage Wide-Pulsed-Latch Digital Circuits for Tolerance of PVT Variations, National Natural Science Foundation of China, 2018-2021, Principal Investigator.
(3) High Density and High Speed Electronic-Photonic SoC, National Key Research and Development Program of China, 2016-2019, Principal Investigator.
(4) Parallel Compiling System for Reconfigurable Processor, Key 863 Program, Minister of Science and Technology of China, 2012-2017, Principal Investigator.
(5) Reconfigurable System-on-Chip for Data-Intensive Video Coding Applications, Key 863 Program, Minister of Science and Technology of China, 2009-2012, Principal Investigator.

(1) Outstanding Faculty Award, SJTU, 2018
(2) Excellent Advisor for National Integrated Circuit Design Contest, 2017
(3) Frist Prize of National Integrated Circuit Design Contest, 2017
(4) First Prize of Science and Technology, awarded by Ministry of National Education, 2014

(1) Projects for Digital Integrated Circuits
(2) Advanced Digital Circuits Design
(3) High Speed Integrated Circuits Design

Jieyu Li, Weifeng He*, Bo Zhang, Liang Qi, Guanghui He and Mingoo Seok, " CCSA: A 394TOPS/W Mixed-signal GPS Accelerator with Charge-based Correlation Computing for Signal Acquisition," IEEE International Solid-State Circuits Conference (ISSCC), 2023.
Shuai Yuan, Yanan Sun, Weifeng He*, Qianrong Gu, Shi Xu, Zhigang Mao, and Shikui Tu, MSLM-RF: A Spatial Feature Enhanced Random Forest for On-Board Hyperspectral Image Classification, IEEE Transactions on Geoscience and Remote Sensing (TGRS), 2022
Bing-Xi Pei, Shi Xu, Zhang Luo, Qin Wang, Ming-Che Lai, and Wei-Feng He*, A Hierarchical Photoelectric Hybrid Packet Switching Network for High Performance Computing, Journal of Optical Communications and Networking (JOCN), 2022
Pengfei Ji, Wenmiao Lin, Wenjia Zhang, Shi Xu, Zhang Luo, Mingche Lai, Qin Wang, and Weifeng He*, Crosstalk Suppression for High-Density Traveling-Wave MZM Array based on Static and Dynamic Combined Analysis and Circuit-Level Designs, Optics Express (OE), 2022
Liukai Xu, Songyuan Liu, Zhi Li, Dengfeng Wang, Yiming Chen, Yanan Sun, Xueqing Li, Weifeng He* and Shi Xu, CREAM: Computing in ReRAM-assisted Energy and Area-efficient SRAM for Neural Network Acceleration, The 59th Design Automation Conference (DAC),2022
Hao Zhang, Weifeng He*, Yannan Sun, and Mingoo Seok, Senior Member, A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022
Jieyu Li, Weifeng He*, Bo Zhang, Guanghui He, Jun Yang and Mingoo Seok, "TICA: A 0.3V, Variation-Resilient 64-Stage Deeply-Pipelined Bitcoin Mining Core with Timing Slack Inference and Clock Frequency Adaption," 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022.
Chuxiong Lin, Weifeng He*, Yanan Sun, Lin Shao, Bo Zhang, Jun Yang, Mingoo Seok, “MPAM: Low-Latency, Near-Threshold-Voltage Multi-Voltage/Frequency-Domain Network-on-Chip with Metastability Risk Prediction and Mitigation,” IEEE Custom Integrated Circuits Conference (CICC), 2022
Hao Zhang;Weifeng He*;Yanan Sun;Mingoo Seok, “An Area-Efficient Scannable In Situ Timing Error Detection Technique Featuring Low Test Overhead for Resilient Circuits”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD),2021;
Chuxiong Lin, Weifeng He*, Yanan Sun, Zhigang Mao, Mingoo Seok, “CDAR-DRAM: An In-situ Charge Detection and Adaptive Data Restoration DRAM Architecture for Performance and Energy Efficiency Improvement,” The 58th Design Automation Conference (DAC), 2021;
Chuxiong Lin, Weifeng He*, Yanan Sun, Bingxi Pei, Pavan Kumar Chundi, Zhigang Mao, Mingoo Seok, “MEDAC: A Metastability Condition Detection and Correction Technique for a Near-Threshold-Voltage Multi-Voltage-/Frequency-Domain Network-on-Chip,” IEEE Journal of Solid-State Circuits (JSSC), 2021;
Hao Zhang;Weifeng He*;Yanan Sun;Member Mingoo Seok, “An Energy-Efficient Logic Cell Library Design Methodology with Fine Granularity of Driving Strength for Near- and Sub-Threshold Digital Circuits”, IEEE International Symposium on Circuits and Systems (ISCAS), 2021;
Jieyu Li;Zihan Lian;Hao Zhang;Weifeng He*;Yanan Sun;Mingoo Seok, “Investigation of Dynamic Leakage-Suppression Logic Techniques Crossing Different Technology Nodes from 180 nm Bulk CMOS to 7 nm FinFET Plus Process”, IEEE International Symposium on Circuits and Systems (ISCAS), 2021;
Hao Zhang;Jieyu Li;Weifeng He*;Yanan Sun;Mingoo Seok, “An Ultra-Low Leakage Bitcell Structure with the Feedforward Self-Suppression Scheme for Near-Threshold SRAM”, IEEE International Symposium on Circuits and Systems (ISCAS), 2021;
Weiyi Liu;Yanan Sun;Weifeng He;Qin Wang, “Design of Ternary Logic-in-Memory Based on Memristive Dual-Crossbars”, IEEE International Symposium on Circuits and Systems (ISCAS), 2021;
Chao Zhang; Jingtong Mo; Zihan Lian; Weifeng He, “High Energy-Efficient LDPC Decoder with AVFS System for NAND Flash Memory”, IEEE International Symposium on Circuits and Systems (ISCAS), 2021;
Zhuojun Liang;Dongxu Lv;Chao Cui;Hai-Bao Chen;Weifeng He;Weiguang Sheng;Naifeng Jing;Zhigang Mao;Guanghui He, “A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021
Chuxiong Lin, Weifeng He*, Yanan Sun, Zhigang Mao, Bingxi Pei, Mingoo Seok, “A Near-Threshold-Voltage Network-on-Chip with a Metastability Error Detection and Correction Technique for Supporting a Quad-Voltage/Frequency-Domain Ultra-Low-Power System-on-a-Chip,” IEEE International Solid-State Circuits Conference (ISSCC), 2020;
Yanan Sun;Weifeng He*;Zhigang Mao;Hailong Jiao;Volkan Kursun, “Monolithic 3D Carbon Nanotube Memory for Enhanced Yield and Integration Density,” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2020;
Yanan Sun, Jiawei Gu, Weifeng He*, Qin Wang, Naifeng Jing, Zhigang Mao, Weikang Qian and Li Jiang, “Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells,” IEEE Transactions on Circuits and Systems--II: Express Briefs (TCAS-II), 2019;
Joao Pedro Cerqueira, Jieyu Li, Hao Zhang, Jiangyi Li, Weifeng He*, Mingoo Seok, “A fW- and kHz-Class Feedforward Leakage Self-Suppression Logic Requiring No External Sleep Signal to Enter the Leakage Suppression Mode,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2019, invited;
P. Ji, J. Gao, W. Xu, Y. Sun, W. He*, and H. Wu, “Electronic-photonic integrated circuit design and crosstalk modeling for a high density multi-lane MZM array,” IEEE International Symposium on Circuits and Systems (ISCAS), 2018;
Y. Sun, W. He*, Z. Mao, H. Jiao, and V. Kursun, “Metallic-CN-removal-tolerant high-yield six-CNMOSFET SRAM cell for carbon-based embedded memory,” IEEE Transactions on Electron Devices (TED), 2018;
W. Jin, S. Kim, W. He*, Z. Mao, M. Seok, “Near- and Sub-Vt pipelines based on wide-pulsed-latch design techniques," IEEE Journal of Solid-State Circuits (JSSC), 2017;
Z. Zhao, W. Sheng, W. He*, Z. Mao, and Z. Li, "A static-placement, dynamic-issue framework for CGRA loop accelerator," Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017;
X. Jin, W. Jin, H. Zhang, J. Jiang, and W. He*, "A 0.2V 2.3pJ/Cycle 28dB output SNR hybrid Markov random field probabilistic-based circuit for noise immunity and energy efficiency," IEEE International Symposium on Circuits and Systems (ISCAS), 2017;
L. Hu, J. Gu, G. He, W. He*, “A hardware-friendly hierarchical HEVC motion estimation algorithm for UHD applications,” IEEE International Symposium on Circuits and Systems (ISCAS), 2017;
J. Gao, Y. Sun, W. He*, and H. Wu, “A cross-layer multi-physics design flow for electronic-photonic integrated circuits,” IEEE Photonics Conference (IPC), 2017;
W. Xu, J. Gao, P. Ji, Y. Sun, W. He*, and H. Wu, “A PAM-4 optical receiver based on a silicon photonic quantizer,” IEEE International Conference on Group IV Photonics (GFP), 2017;
L. Chen, Y. Sun, and W. He*, “Low-power single-phase clocked redundant-transition-free flip-flop design with conditional charging scheme,” IEEE International Conference on ASIC (ASICON), 2017, invited;
Y. Sun, W. He*, Z. Mao, H. Jiao, and V. Kursun, “Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors,” IEEE International Conference on ASIC (ASICON), 2017, invited;
W. Jin, G. He, W. He*, and Z. Mao, "A 12-bit 4928 × 3264 pixel CMOS image signal processor for digital still cameras," Integration, the VLSI Journal, 2017;
W. Jin, W. He*, J. Jiang, H. Huang, X. Zhao, Y. Sun, X. Chen, and N. Jing, “A 0.33V 2.5μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130nm CMOS,” Integration, the VLSI Journal, 2017;
W. Jin, S. Kim, W. He*, Z. Mao and M. Seok, "In situ error detection techniques in ultralow voltage pipelines: Analysis and optimizations," IEEE Transactions on Very Large Scale Integration Systems(TVLSI), 2017;
Y. Sun, W. He*, Z. Mao, and V. Kursun, “Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic,” Microelectronics Journal, 2017;
Y. Sun, W. He*, Z. Mao, H. Jiao, and V. Kursun, “High-yield and robust 9T SRAM cell tolerant to removal of metallic carbon nanotubes,” IEEE Transactions on Device and Materials Reliability, 2017;
W. Jin, S. Kim, W. He*, Z. Mao, M. Seok, “A 0.35V 1.3pJ/cycle 20MHz 8-bit 8-tap FIR core based on wide-pulsed-latch pipelines,” IEEE Asian Solid-State Circuits Conference (A-SSCC), 2016;
Liang Hong;Weifeng He*;Guanghui He;Zhigang Mao, “Area-efficient HEVC IDCT/IDST architecture for 8K x 4K video decoding”, IEICE Electronics Express, 2016
Z.Yan, G.He, W.He*, S.Wang, Z.Mao, “High performance parallel turbo decoder with configurable interleaving network for LTE application,” Integration, the VLSI Journal, 2016;
J. Gao, Y. Sun, W. He* and H. Wu, “A cross-layer multi-physics design flow for electronic-photonic integrated circuits,” IEEE Photonics Conference (IPC), 2016;