Center for Advanced Electronic Materials and Devices

  • Name:程秀兰
  • Title:Professor
  • Office:Rm. 103, Microelectronic Building
  • Office Phone:86-21-34208269
  • Website:

Research Field

(1) Silicon photonic devices and fabrication
(2) Nano-biochips for trace-level organic molecular detection
(3) Design and simulation of advanced semiconductor devices (e.g., Non-volatile memory)


1999-2002: Ph.D. in Microelectronics and Solid Electronics, Center of Information Storage, Shanghai Jiao Tong University, Shanghai, China
1993-1996: M.S. in Material Science and Engineering, Dept. of Metallurgy, Chongqing University, Chongqing, China
1989-1993: B.S. in Material Science and Engineeri

Work experience

2013-Present: Prof., Execute Deputy Director, Center for Advanced Electronic Materials and Devices (AEMD), School of Electronic, Information and Electrical Engineering, Shanghai Jiao Tong University, Shanghai, China
2009-2010: Visiting Scholar, Depar. of Bioengineering, University of California at Berkeley, Berkeley, CA, USA
2008-2009: Visiting Researcher, Depart. of Physics, University of Arkansas, Feyettevelle, AR., USA
2003-2013: Associate Prof., School of Microelectronics, Shanghai Jiao Tong University, Shanghai, China
2002-2003: Research Engineer, Depart. of Logic Technology Development, Semiconductor Manufacturing International Co. Ltd., Shanghai, China
2002-2002: Thin Film Engineer, Depart. of Zhangjian 8" Project, Shanghai Belling Co. Ltd., Shanghai, China
1996-1999: Engineer, Depart. of Heat Treatment, Qishuyan Locomotive and Rolling Stock Institute, National Ministry of Railway, Changzhou, China


1. 2016-2019: Research on high density optoelectronic integration and system level optical switching technology (Subproject, "High Performance Computing"-The 13th Five-Year Key Research and Development Plan, National Ministry of Science and Technology)
2. 2016-2018: High speed spatial light modulator based on silicon graphene composite structure (Participating, National Science Foundation)
3. 2014-2016: Performance test of dry etching and cleaning process of fluorine containing electronic gas products (Industry cooperative project)
4. 2014-2016: Development of advanced silicon dry etching process (subproject, "Development and industrialization of gate dry etching system ", National 02 Key Special Project)
5. 2012-2013: Research on the third generation nanopore DNA sequencing technology based on carbon materials(Subproject, Development on new generation sequencing system and accessory products, National '863' High Tech Program)

Awards and Honors

2003: Outstanding employee, Semiconductor Manufacturing International Co. Ltd.
2004: Outstanding Faculty, Shanghai Jiao Tong University
2013: Outstanding Faculty, Shanghai Jiao Tong University


1. Undergraduate Courses
(1) Semiconductor Physics and Device
(2) Semiconductor Fabrication Technology
(3) Integrated Circuit Packaging and Test
(4) Introduction to Microelectronics

2. Graduate Courses
(1) Semiconductor Physics and Device
(2) Advanced Microelectronic Processing Technology
(3) Microelectronic Yield and Reliability
(4) Advanced Micro/Nano Fabrication Technologies and Applications


(1) D. Ma, X. Wang, Y. Shen, X. Cheng*, Simulation of 1.0 m CMOS Baseline Process at AEMD of Shanghai Jiao Tong University, 2015 International Conference on Microelectronics and Information Technology (ICMIT 2015), Sanya, P.R. China, 2015.12 :2583-2586
(2) Xufeng Yu, Xiulan Cheng*,Pengyu Lv, A New SERS Substrate Based on TiO2 Nanorods Thin Film Assembled Gold Nanoparticles, 2014 Asia-Pacific Materials Science and Information Technology Conference (APMSIT 2014) /Applied Mechanics and Materials , Shanghai, P.R. China, 2014, 12.13-12.14.
(3) Jun Lee, Xiulan Cheng*, Xufeng Yu, Pengyu Lv, Didi Ma, A SERS Substrate based on TiO2 Nanowires Coated with Au Nanoparticls, Journal of Functional Materials and Devices, 2014, 20(1):1-4.
(4) Zhong-Xian Li, Xiu-Lan Cheng*, Zhi-Min Wang*, Sub 10nm Nanopore Sculpturing with Focused Electron Beam on Single Layer Graphene Oxide Film, Adv. Mater. Res. , 2013, 631-632: 154-159.
(5) Kai-Yu Wu, Xiu-Lan Cheng*, Luke P Lee,Intra-particle coupling and plasmon tuning of multilayer Au/Dielectric/Au nanocrescents adhered to a dielectric cylinder, Nanotechnology, 2012, 23 (5):1-10.
(6) Lingzhi Chen, Xiulan Cheng*, Zhimin Wang, Cantilever beam biological detection technology based on embedded carbon nanotubes, Information Technology, 2011, (7):14-16.
(7) Weihua Tian, Kaiyu Wu, Xiulan Cheng*, Xiaodong Chen, Rui Chen, Ying Wang, Preparation and Analysis of the Au-SiO2 Multi-layer Nanospheres as High SERS resolution Substrate, SPIE Asia Communications and Photonics Conference and Exhibition (SPIE ACP 2011), Shanghai, China, 2011, 11.13-11.16, Proc. Proc. SPIE 8311, 83110K
(8) Yuan Zeng, Hai-jun Tan, Xiu-Lan Cheng*, Rui Chen, Ying Wang, A Highly Sensitive Biological Detection Substrate based on TiO2 Nanowires Supporting Gold Nanoparticles, SPIE Asia Communications and Photonics Conference and Exhibition (SPIE ACP 2011), Shanghai, China, 2011, 11.13-11.16, Proc. SPIE 8311, 83110H
(9) Fulong Zhuang, Da Chen, Dong Xu, Xiulan Cheng*, Strain sensors based on layer-by-layer self-assembly carbon nanotube thin films, Journal of Functional Materials and Devices, 2010, 16(6): 610-616.
(10) Jingzhou Si, Xiulan Cheng*, Lingzhi Chen, Nanopore DNA single molecule sensing method and synthetic nanopore fabrication, Int. J. Biomed. Eng., 2009, 32(6): 353-358.
(11) Junqing Zhou, Xiulan Cheng*, Effect of Thermal and Electrical Properties of Materials on the Power Consumption of Phase Change Memory, Journal of Functional Materials and Devices, 2009.15(6):530-536.
(12) Ye Huang, Xiulan Cheng*, Design and Analysis of SEU/SET Hardened D Flip—Flop, Semiconductor Technology, 2009 ,34: 69-72.
(13) Zhengxing Gao, Xiulan Cheng*, Design and Research of a Novel High Voltage Power Device~SON—LDMOS, Chinese Journal of Electron Devices, 2009, 32: 291-295.
(14) Wen Yin, Xiulan Cheng*, Zhigang Feng, Design and simulation of a high performance Phase Change Memory cell based on GaSbTe, Journal of Functional Materials and Devices,2008, 14: 988-994.
(15) Cheng, X.*,Yin, W., Feng, Z., Liang, T. Simulation on A Novel Ga-doped Phase Change Memory for Next Generation Embedded Non-Volatile Memory Application, 2008 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2008, Cambridge, MA, 2008, 5.5-5.7: 43-48.
(16) Wen Yin, Xiulan Cheng*, Technology and status of embedded phase change memory, Information Technology,2008, (05): 169-172 ,174.
(17) Hua, S., Cheng, X.*, Jin, T. A Novel Advanced Process Control for Semiconductor Manufacturing: Dual Proximate Inverse System Feedback Control, 2008 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2008, Cambridge, MA, 2008, 5.5-5.7:167-172
(18) Qian, F., Cheng, X.*, et al. Thermal-Mechanical Simulation and Analysis on Structural Caused Package Induced Stress in Stacked Chip Scale Package, Journal of Shanghai Jiaotong University. (S2): 139-143 (2007).
(19) Shaohua Fang, Xiulan Chen*, Investigating the effect of doping amorphous silicon nitride on retention characleristics Of SONOS device, ACTA PHYSICA SINICA, 2007, 56: 6634-6641.
(20) Shaohuao Fang, Xiulan Cheng*, High Sensitive Biosensors, Micronanoelectronic Technology, 2007, (1): 34-38.
(21) Shaohua Fang, Xiulan CHeng*, Research Progress of SONOS Nonvolatile Memory Device, Chinese Electronic Devices,2007, 30: 1211-1215.
(22) Zheng Li, Xiulan CHeng*, Novel Photomask Manufacturing Rule Check Method and System, Semiconductor Technology, 2007, 32: 238-240.
(23) Cheng, X.*, Zhi, C. et al. Optimizing Post Cleaning of Tungsten Contact CMP to Improve the Yield of Logic Products with Copper Interconnect, IEEE ICSICT-2006 (The 8th International Conference on Solid-State and Integrated-Circuit Technology), Shanghai, China, 2006,10. 23-10.26, Shanghai, China: 51-353.
(24) X. Cheng*, Y.Z. Fu, C. Yang, Y. Chen, Development of an industry-oriented graduate course on microelectronic packaging in China, Proceedings of the ASME InterPack Conference 2007, Vancouver, Canada, 2007, 7.8-7.12, 1:429-433.
(25) Cheng, X.*, Huang, Y., Effect of the Properties of Gold Wire on the Ability of Low-looped Wire Bonding, IEEE ICEPT2006 (7th International Conference on Electronics Packaging Technology), Shanghai, China, 2006, 8.26-8.29: 410-422.
(26) Cheng, X.*, Huang, Y., Study on the Low-looped Ability of Forward and Reverse Looping Methods of Gold Wire Ball Bonding for Stacked Die Package Application, IEEE ICEPT2006 (7th International Conference on Electronics Packaging Technology) , Shanghai, China, 2006, 8.26-8.29: 650-652.