Zhilei Xu of SEIEE SJTU Published Important Innovations in Hardware-Accelerated Privacy Computing on ISCA 2022

Zhilei Xu, Associate Professor of Qing Yuan Research Institute,SEIEE,SJTU together with his collaborators, recently presented their paper on “International Symposium on Computer Architecture (ISCA)”, a top international conference in the Computer Architecture area. The paper titled “PPMLAC: High Performance Chipset Architecture for Secure Multi-Party Computation”, of which Zhilei Xu is the corresponding author, creatively designed an approach to accelerate Secure Multi-Party Computing by hardware chipsets. This important innovation in Privacy Computing area has been accomplished by joint work among Qing Yuan Research Institute at Shanghai Jiao Tong University, Institute for Interdisciplinary Information Sciences (IIIS) at Tsinghua University, and Shanghai Zi Xian Technology.

1、Research Background

Secure Multi-Party Computation (MPC) is an approach to Privacy Computing: MPC participants, holding their own private data, collectively compute the result of some function that depends on every party’s data, while avoiding leaking any party’s data to any other participant. This approach makes data “usable but not visible”: each party’s private data is only used for computing the function’s final result, but cannot be owned or sniffed by any other party.


The MPC problem was first proposed and theoretically solved by Turing Award Laureate Chi-Chih Yao in early 1980s. After decades of development and contributions by many computer scientists and mathematicians, MPC has seen improvements in several aspects like computation complexity, communication complexity, and there are some applications of MPC in such privacy-critical situations as finance and health areas.

But existing software-based implementations of MPC are very sensitive to network latency, thus perform poorly under realistic cross-data-center network conditions, and are not suitable for big data and complex models.

2、Research Highlights

The paper published on ISCA 2022 solves the performance problem of MPC under realistic network conditions. With his collaborators, Associate Professor Xu discovered that the Secret-Sharing-based MPC, a widely-used MPC implementation, can be improved by introducing a hardware-based minimal trust root, resulting in a hardware-software mixed system without the performance bottleneck. The innovation replaced the frequent bi-directional communications of traditional MPC with one-way traffic, which enables optimizations like asynchronous communication and pipelining, therefore greatly accelerates MPC and makes it totally insensitive to network latency. Based on this finding, Xu and collaborators took advantage of hardware chip’s non-modifiability and asymmetric cryptography to construct a special chipset architecture called “PPMLAC” to accelerate MPC. This hardware chipset accelerates MPC computation of complex machine learning models by orders of magnitudes of improvements. For instance, the PPMLAC prototype FPGA chipset finished ResNet inference job (a classical object detection model) under 5 seconds under realistic network conditions, which takes several hours by SPDZ, a widely-used software MPC implementation.

The hardware trust root introduced by the PPMLAC architecture is only used for MPC multiplications, a very basic operation, so it’s very easy to implement robustly and securely on the chipset, and only adds a very narrow attack surface. This chipset architecture is robust against several common attacks, including side-channel attacks.

The PPMLAC chipset can accelerate all common Privacy-Preserving Machine Learning, Big Data, and Statistical applications, and can expand the applicability of Privacy Computing. Through this and many other follow-up works, Xu and collaborators aim to contribute to the big data industry and the protection of people’s data-privacy in China.

3、About ISCA

ISCA (International Symposium on Computer Architecture) is one of the three top conferences in the Computer Architecture research area, the other two being MICRO and HPCA. Founded by ACM SIGARCH and IEEE TCCA in 1973, ISCA has been the venue of many ground-breaking innovations in the semiconductor industry by Google, Intel, Nvidia etc. The official sites show that the acceptance rate of ISCA has constantly been below 20%. ISCA 2022 only accepted 67 papers out of 398 submitted (16.83%), with only 8 papers from institutes in mainland China.

4、About the author

Associated Professor Zhilei Xu, the paper’s corresponding author, graduated from Massachusetts Institute of Technology (PhD) and Tsinghua University (Bachelor), and worked in Google and Facebook. He has long been working in the research areas of Programming Languages, Operating Systems and Distributed Systems, and has profound knowledge of both theory and practices. He joined the Qing Yuan Research Institute at Shanghai Jiao Tong University in December 2021. He runs the Systems Security and Reliablity Research Group, focusing on Programming Languages, Information Security, Software Reliability and Security, Operating System and Distributed Systems.

Link to the paper: https://dl.acm.org/doi/10.1145/3470496.3527392

[ 2022-09-17 ]