课程名称 (Course Name) ： Advanced Computer Architecture

课程代码 (Course Code）： ES26037

学分/学时 (Credits/Credit Hours)：3/48

开课时间 (Course Term )：  Fall

开课学院（School Providing the Course）:  Micro/Nano electronics Department

任课教师（Teacher）:   Zhu Yongxin

课程讨论时数（Course Discussion Hours）:  2

课程实验数（Lab Hours）:    6

课程内容简介(Course Introduction):

This course is the basic module for graduate students in the areas of computer architecture, integrated chip design and system design. The course also fits the students in the areas of electronic engineering and information engineering who are interested in computer and digital system design. The course will cover at least the quantitative design and evaluation approach to computer and digital system design, principles of instruction set design, instruction level parallelism implementation, cache and memory hierarchy architecture and design, principles and features of major I/Os and interconnections, novel processor architectures including many core and GPU processors, principles of cloud computing and big data processing platform as well as cutting edges of computer and digital system design trends.

教学大纲(Course Teaching Outline):

 

Chapter 1 Basic concepts of computer architecture, Basic quantitative analysis of computer architecture (6 hours)

1)        Concurrent motivations for research on computer architectures

2)        The basic concepts of computer architecture

3)        The quantitative evaluation methods and metrics

4)        Amdahl’s law

5)        Analysis of system overhead

Chapter 2 Memory hierarchy and virtual machines (6 hours)

1)        The basic structure of the cache

2)        Cache Optimization

3)        DRAM memory technology and optimization

4)        The virtual machine structure and impacts on virtual memory

5)        ARM Cortex-8 memory hierarchy

6)        Intel Core i7 memory hierarchy

Chapter 3 Instruction Level Parallelism (ILP) principles and techniques (12 hours)

1)        MIPS instruction set

2)        MIPS pipeline

3)        Instruction dependencies

4)        Software optimization based ILP

5)        The branch prediction

6)        TOMASULO scheduling algorithm

7)        Limitations of ILP

8)        Simultaneous multithreading (SMT)

Chapter 4 Data level Parallelism (DLP), Vector machine architecture and Graphics processor unit (GPU) architecture (6 hours)

1)                      Data level parallelism in Single Instruction Multiple Data  (SIMD) architecture

2)                      Data level parallelism in vector machine architecture

3)                      Data level parallelism in graphics processor

4)                      Programming paradigm of vector machine architecture

5)                      Programming paradigm of SIMD/GPU architecture

Chapter 5 Thread level parallelism (TLP) and cache (Cache) coherency protocol (6 hours)

1)        The principles of thread level parallelism and symmetric multiprocessors

2)        The principle of distributed shared memory

3)        The cache coherency principle

4)        The snooping protocol cache coherence protocols and examples

5)        The directory based cache coherence protocol and examples

6)        Data synchronization and memory consistency principle

Chapter 6 Request level parallelism (RLP) parallel principle and warehouse computing (4 hours)

1. Request level parallelism (RLP) principle and the concept of Warehouse Computing

2. Warehousing computing examples from Google

3. Challenges of warehouse computing design

4. Cloud computing features relevant to warehouse computing

5. Big data applications for warehouse computing

课程进度计划(Course Schedule):

Week 1-2: Fundamentals of Computer Architecture (Ch. 1) 6 lectures

Week 3-4: Cache and Memory systems (Ch. 2) 6 lectures

Week 5-8: Pipelining & ILP & Scheduling (Ch. 3) 12 lectures

Week 8:   Lab1 on pipelining and instruction set parallelism, 3 hours

Week 9-10: GPU and vector machines (Ch. 4) 6 lectures

Week 10:   Lab 2 on whole processor, 3 hours

Week 11-12: Multiprocessors and TLP (Ch 5) 6 lectures

Week 13-14: Computer warehouse system and reliability (Ch6) 4 lectures

Week 15: Students’ presentations and discussion, 2 hours

Week 16:  Review

Week 17:  Written exam

课程考核要求(Course Assessment Requirements)：

5 problem sets，2 lab reports

Final written exam in 17^th  week.

参考文献(Course References)：

1. John L. Hennessy and David A. Patterson, Computer architecture: a quantitative approach, (ISBN: 9787111364580), Elsevier Science Ptd Ltd, 5th edition, 2012
2. David Patterson and John Hennessy , Computer Organization and Design, The Hardware/Software Interface, Fourth Edition, ARM Edition, 2010
3. David Patterson and John Hennessy, Computer Organization and Design, The Hardware/Software Interface, Fourth Edition, 2008

预修课程（Prerequisite Course）

   Computer Organization, Digitial Circuits